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发明名称
LOGIC CIRCUIT
摘要
PURPOSE:To reduce the number of components in the logic circuit using isolated type FET, to reduce the power consumption, and to constitute the circuit configuration suitable for integration and operationable stably even at lower frequencies.
申请公布号
JPS5366357(A)
申请公布日期
1978.06.13
申请号
JP19770135649
申请日期
1977.11.14
申请人
TOKYO SHIBAURA ELECTRIC CO
发明人
SUZUKI YASOJI
分类号
G11C19/28;H03K19/017;H03K19/096
主分类号
G11C19/28
代理机构
代理人
主权项
地址
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