发明名称 Setting circuit for electronic timepiece - using setting pulses with variable pulse train frequency altered in stages
摘要 <p>The setting circuit is for an electronic timepiece with an oscillator, a frequency divider and a counter network, supplying signals to a digital display. The circuit uses setting pulses with a variable pulse train frequency, fed into the counter network. A setting pulse generator automatically supplies a variable setting pulse train frequency after selection of the time setting operation. The pulse train frequency may be varied in stages and the setting pulse generator pref. comprises a voltage-controlled oscillator (20). The control input (21) of the latter is coupled to a time constant circuit (R1, C) the capacitor (C) of which is bypassed by a setting switch (S) for normal running of the timepiece.</p>
申请公布号 DE2654305(A1) 申请公布日期 1978.06.01
申请号 DE19762654305 申请日期 1976.11.30
申请人 SIEMENS AG 发明人 STETTMAIER,HELMUT,DIPL.-MATH.
分类号 G04G5/02;(IPC1-7):04C9/00;04C3/00 主分类号 G04G5/02
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