| 发明名称 |
MEMORY UNIT POSSESSING AUXILIARY LOOP |
| 摘要 |
PURPOSE:To secure a conversion of the pulse row into a correct sequence and tu thus to avoid the complication of the mechanism as well as the cost increase even in case multiple chips are operated simultaneously, by using a simple and single pulse row converter circuit. |
| 申请公布号 |
JPS5361235(A) |
申请公布日期 |
1978.06.01 |
| 申请号 |
JP19760136309 |
申请日期 |
1976.11.15 |
| 申请人 |
HITACHI LTD;NIPPON TELEGRAPH & TELEPHONE |
发明人 |
YOSHIZAWA SHIGERU;SAITOU NOBUO |
| 分类号 |
G11C11/14;G11C11/24;G11C19/00;G11C19/28;G11C27/04;G11C29/00;G11C29/04 |
主分类号 |
G11C11/14 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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