| 摘要 |
A digital signal processor adapted for use in small, lightweight radar-guided missiles. The processor includes a scratch pad register section, an arithmetic-logic unit and a control section arranged to enable data stored in two different storage elements included in such register section to be operated on by the arithmetic-logic unit, the result of such operation to be stored in a third storage element included in the register section and the contents stored in a program counter register to be incremented by one or jumped to a predetermined address selectively in accordance with the result of the arithmetic operation, all during the execution of a single one of a plurality of stored control instructions.
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