发明名称 DIGITAL PLL CIRCUIT
摘要 PURPOSE:The output of a PLL is so constituted that the steady jitters are made small against the changing point of an input signal without changing a followup speed, and the number of parts of the circuit is reduced, thereby realizing the simplification of the circuit.
申请公布号 JPS5352041(A) 申请公布日期 1978.05.12
申请号 JP19760126854 申请日期 1976.10.22
申请人 NIPPON ELECTRIC CO 发明人 AKAGI YOSHIYUKI;OKANO YOSHIMITSU
分类号 H03L7/06;H03L7/00 主分类号 H03L7/06
代理机构 代理人
主权项
地址