发明名称 |
COUNTER USING SHIFT REGISTER |
摘要 |
PURPOSE:To obtain a high-speed counter circuit which is suited for IC formation by constituting the logical circuit to which a necessary bit output of a shift register is supplied with a serial circuit of MOS transistor which detects the conduction or non-conduction synchronizing with the clock signal. |
申请公布号 |
JPS5350964(A) |
申请公布日期 |
1978.05.09 |
申请号 |
JP19760125461 |
申请日期 |
1976.10.21 |
申请人 |
TOKYO SHIBAURA ELECTRIC CO |
发明人 |
SASAKI MINORU |
分类号 |
H03K23/52;H03K23/54;(IPC1-7):03K23/02 |
主分类号 |
H03K23/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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