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发明名称
CLOCK ALTERNATION CONTROL SYSTEM
摘要
PURPOSE:Two independent clock and source are provided and two CPUs are equipped with distributor circuits respectively, thereby switching more than two kinds of clocks of a high-speed operation system without resetting the system.
申请公布号
JPS5348428(A)
申请公布日期
1978.05.01
申请号
JP19760117824
申请日期
1976.09.29
申请人
FUJITSU LTD
发明人
OOTA EIKICHI
分类号
G06F11/18;G06F1/04;G06F3/00;G06F9/52;G06F13/00;G06F13/42;G06F15/16;G06F15/177
主分类号
G06F11/18
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