Integrated injection logic circuit having reduced delay

摘要

An integrated injection logic storage element having a minimum delay time. Means for steering input data into the circuit are provided. These means are coupled to another means for selectively gating the input data through the circuit. The means for selectively gating is responsive to a clock pulse. A third means for providing an output storage latch and having multiple outputs is coupled to the means for selectively gating. At least one of the multiple outputs is coupled to an output of the means for selectively gating thereby providing an output which has a delay time which is less than another one of the multiple outputs which is not coupled to the means for selectively gating.