Phase locked loop decoder

摘要

A phase locked loop decoder for decoding digitally encoded data is disclosed in which each incoming data bit is synchronized to a clock frequency and a derived signal representative of the data cell width is varied in accordance with a derived phase error signal to compensate for bit shift and for data cell width variation which may be present in the incoming data. The phase error signal is a pulsed waveform having a leading edge synchronized with the occurrence of each data transition and a pulse width reprsentative of the phase error of the data with respect to the clock. The decoder will detect and decode data transitions having bit shifts of up to plus or minus 50 percent of the bit cell period.