| 摘要 |
<p>1275210 Automatic exchange systems INTERNATIONAL BUSINESS MACHINES CORP 19 June 1970 [20 June 1969] 29789/70 Heading H4K An interface 1 between a computer 3 and a plurality of junctors 2 each of which includes a plurality of relays, n1-n8 comprises a store 5 having one cell m1-m8 in respect of each of the relays in a junctor and a number of cells t, r in respect of a control word which is operative on all those m cells that may be concurrently marked. The control word may be 11 meaning complete updating of the junctor, 10 meaning the setting of some relays, 01 meaning the resetting of some relays or 00 meaning that the condition of the relays should be transmitted to the computer. In operation the computer starts the interface clock counter 10 over lead D and writes a word into store 5. The parity (bit P) is immediately checked in circuit 11 whereby fault detector 12 is enabled to signal the computer on lead F if there is any fault. The counter is stopped and the contents of store 5 are transmitted to the computer which thereafter resets the counter. If there is no fault, the address in x 1 ... y 3 of the required junctor is decoded at 6 and the interface thereby connected via contacts J1-J8 to the relevant junctor. During time phase t2 the contents of t-m8 are decoded in circuits 7 of which there is one per relay in a junctor. For example, with the control word 11, a 1 bit in m1 causes transistor driver 17 to apply negative battery to output lead 19 thus energizing relay n1 in the junctor, on the other hand if m1 contains a 0 bit transistor driver 18 applies a small positive battery via a Zener diode (Fig. 2, not shown) to lead 19 thus releasing n1. Similarly for each of the cells m2-m8. With control words 01 and 10 only 1 bits in m produce a significant result. The effect of control word 00 is mentioned below. During phase t3 the circuits 7 are cut-off while circuits 22 (which incorporate transistors and Zener diodes, Fig. 3, not shown) measure the potentials on their associated leads 19. The potentials are compared with the control word and the m bits so as to produce a fault output via fault detector 12 if the relevant n relays have not operated correctly. If the control word is 00 circuits 26-28 are enabled during t3 to convey the conditions of the n relays (as determined by the potentials measured on leads 19) to the store 5. The fault detector is enabled (via circuit 49) by control word 00 so as to call in the computer but as there is no real fault i.e. leads 44, 48 are not marked, the computer knows that it is merely being informed of the n relay conditions in the defined junctor. The counter is reset by the computer as before. For other control words under no fault conditions, the counter rests itself at t5, having cleared all the stores during t4. Bi-stables are used as the cells in store 5.</p> |
