| 摘要 |
1507079 Testing telecommunications system DE STAAT DER NEDERLANDEN TE DEZEN VERTEGENWOORDIGD DOOR DE DIRECTEURGENERAAL DER POSTERIJEN TELEGRAFIE EN TELEFONIE 24 June 1975 [17 July 1974] 26750/75 Heading G1U In monitoring the quality of a radio relay link, the average noise power/minute and average baseband load/minute are measured and compared to predetermined reference levels, the exceeding of which is signalled. For noise measurement, a filter 3 defines a 7 kHz band about the appropriate frequency (4765 kHz or 4830 kHz for 960 or 1800 channel systems respectively), this signal is mixed with an appropriate local oscillator 5 signal to provide a 65 kHz imput to an i.f. stage 6, providing variable gain (60-100 dB) and noise band width definition (3À1 kHz). To measure instantaneous noise power, integrated square-law generators 11, 12 are used. Since each of these has only 25 dB dynamic range, two alternate channels are provided. At low levels comparator 16 connects resistor 17 to the following integrator 13, such that an amplifier 15 (20 dB) is inserted into the measurement. At levels 20 dB above the minimum input, comparator 16 switches over to resistor 18, and square-law generator 12 is brought into operation. The values of the resistances 17, 18 are chosen such that their ratio equals the square of the amplifier gain, ensuring that the change-over provides a continuous response function over 45 dB of dynamic range. The integrators 13, 14 use two capacitors alternately. allowing the non-used one to discharge during the period of one minute in which the other is charging. A comparator 19 has a variable low level reference and drives a l.e.d. 36. The comparator 20 responds to a higher fixed reference. To measure the baseband load, a baseband filter 26 comprising highpass, low-pass and pre-emphasis filter 33-35 provides a signal to a thermocouple square-law generator 27, integrator 28 and comparators 29-32 having references at the nominal level, Œ 3 dB and + 6 dB. All the comparator outputs drive l. e. d.'s and their outputs are fed to a buffer register 37 which is up-dated at the end of every one minute period. A divide by 3000 clock 25 derives timing signals for the register and integrators from the 50 Hz mains frequency. |
