LF pulse generation for multiplexers - uses HF pulses to provide correction to LF

摘要

The generation of low frequency pulses from a high frequency source in multiplexing systems includes a facility to generate a defined number of high frequency pulses for input to a phase locked loop. The central unit receives the multiplexer clock signals (Tm) and processes them over a frequency divider (PT) and counter (Z1). The central unit outputs a preselected number of pulses to the decentralised unit each main period. Counters (22, 23) together with a bistable (FF) and NAND gate (N) enable additional correcting pulses to be added to provide the output over a divider (Z4) to the phase locked loop (PLL).