High speed counter with programmable frequency division - uses auxiliary counter stage to minimise delay associated with clock inhibition during preset cycle

摘要

A high speed clock controlled counter includes a facility for programming a specific frequency division ratio. The basic frequency division is provided by a binary counter (2) that is coupled to a selector (1) to apply a preset condition. The counter outputs (QA--QD) are coupled to a decoder (3) that recognises a specific combination. At the end of each cycle the preset is enabled (L) and the clock input (20) inhibited. In order to speed up the counter cycle, an auxiliary counter (4) is included. This counter does not influence the preset cycle, but minimises delay associated with inhibition of the clock input. A control pulse generator (7), preset pulse generator (6) and clock gate (5) complete the system.