| 发明名称 |
ERASING METHOD OF ERASABLE ROM |
| 摘要 |
<p>PURPOSE:To erase effectively and accurately in a short time by providing an address designation circuit and a decision circuit at the input side and the output side of a read-only memory respectively.</p> |
| 申请公布号 |
JPS5330838(A) |
申请公布日期 |
1978.03.23 |
| 申请号 |
JP19760105033 |
申请日期 |
1976.09.03 |
| 申请人 |
FUJITSU LTD |
发明人 |
KISHI TOSHIYUKI |
| 分类号 |
G11C17/00;G11C16/02;G11C16/34 |
主分类号 |
G11C17/00 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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