GENERATING A PSEUDO-RANDOM SEQUENCE OF ETA-BIT WORDS

摘要

1504806 Pseudo random pulse sequence generators PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 17 March 1975 [20 March 1974] 10941/75 Heading G4D The invention concerns an arrangement for generating pseudo random sequences of the kind supplied by feedback shift registers but supplying n-bit words in parallel instead of individual bits in series. The main register R1, which has no shifting function, has m + n stages. At each clock pulse the last n stages are read to provide an n-bit output word to a register R2. The same n-bit word addresses a read only memory M which delivers a corresponding m + n bit word to a register ADDR1. The other m stages of the main register R1 are read into the last m stages of another register ADDR2 (i.e. shifted six steps to the right) and the contents of ADDR1 and ADDR2 are added modulo-2 and replace the contents of the main register R1 whereupon the cycle is repeated. The result is that at each clock pulse the register R 1 delivers simultaneously the n bits which would have occurred consectuvely from an m stage feedback shift register of the conventional type and then immediately changes to a state n steps later in the usual sequence. The arrangement operates much faster and delivers complete words needed for ciphering in a transmission system.