发明名称 BUFFER MEMORY CONTROLLING SYSTEM
摘要 PURPOSE:To shorten the operation time with respect to probability by selecting data by an arithmetic unit at the time of hit of either of two data busses included in two ways and detecting hit by next two ways at the time of mishit. CONSTITUTION:An 8-byte 4-way data bus from data #0 to #3 in a buffer memory BS 21 is divided to first four bytes and latter four bytes through align circuits 231 to 234, and only first bytes are used at the time of 4-byte operation. At the time of 8-byte operation, first four bytes of circuits 231 and 233 are selected by MPX0 and MPX2, and latter four bytes are latter four bytes are selected by MPX1 and MPX3. When an 8-byte operation instruction is detected by an 8B instruction detecting circuit 40, 8-byte data of data #1 and #2 in the BS are completely selected from four 4-byte data busses. Consequently, the operation time is 1tau at the time of hit of either of data #0 and #2, and the operation time is 2tau at the time of mishit because of selection of 8-byte data #1 and #3 in the next period tau but the probability of the occurrence is 50%, thus shortening the operation time.
申请公布号 JPH02268328(A) 申请公布日期 1990.11.02
申请号 JP19890091054 申请日期 1989.04.11
申请人 FUJITSU LTD 发明人 KITANO YUKIHIKO
分类号 G06F12/08;G06F5/06;G06F7/00;G06F7/57 主分类号 G06F12/08
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