| 摘要 |
PURPOSE:To reduce number of elements and power consumption by connecting an inverted output of each FF to an input of a switch whose input is provided separately, connecting an optional switch input terminal to a switch output terminal and inputting this output to the 1st stage of the FFs connected in cascade. CONSTITUTION:A clock signal 20 is inputted to a terminal C of FFm1-mj. A desired frequency division is taken 1/j, and an input terminal and an output terminal of the switch S2 to which the inverted Q output of the FFmj are connected. Since the inverted Q output of the FFmj becomes a data input to the FFm1 of the stage, j-stage of ring counter is formed. Further, the inverted Q output of the FFmj becomes the frequency division output of 1/j and its output becomes a desired frequency division output via the switch S2 and extracted externally. Thus, the number of elements and power consumption are reduced.
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