| 摘要 |
PURPOSE:To shorten the access time and to improve the performance of a bus control system for an information processor which uses a common bus, by providing a signal which switches an operation mode between an arithmetic processor and a bus control part. CONSTITUTION:An arithmetic processor 3 has two modes for a common bus 1, and the selection between both modes is informed to a bus control part 21 by the signal of an operation mode signal line 100. Then the switching is carried out for control of the bus using right. When the reading is ended with data given from a main memory 2 of an input/output controller 4 in a certain mode, it is possible to accept the next bus using right. In this case, signals are transmitted among bus using right request signal lines 41 and 51 as well as bus using right answer signal lines 42 and 52 of input/output controllers 4 and 5, a bus using right request signal line 31 and a bus using right answer signal line 32, respectively. Thus a desired operation mode is set. Then it is possible to operate the bus 1 as if it has artificially two buses. |
