| 摘要 |
A detector for detecting a delta modulated signal includes a timing circuit, a counter and a decoder arranged to detect a delta modulated signal in electrically noisy environment. The timing circuit is used to provide a timing signal of a predetermined time interval over which the counter counts the transitions present in the delta modulated signal. The counter is used for counting the digital bit occurrences of the delta modulated signal within the predetermined time interval. The decoder responds to the timing signal and receives the count signals from the counter and provides a binary signal of first state when the count signal indicates the number of bit occurrences of the delta modulated signal is above a predetermined high level of count or below a predetermined number of low count and provides a binary signal of a second state when the count signal indicates that the number of the digital bit occurrences occur between the predetermined high level of count and the predetermined low level of count. The detector is further provided with a latch circuit which responds to the output of the decoder and a code detect signal representing detection of a predetermined code signal in delta modulated signal. The latch circuit is used to provide an output signal in response to the binary signal of the first state from the decoder and the code detect signal to signify proper reception of delta modulated signal. The above described detector may be advantageously used in a receiver for receiving a scrambled or unscrambled incoming delta modulated digital data signal. |
