发明名称 PARALLEL COMPUTER SYSTEM FOR CHECKING SERIAL PERIODIC REDUNCANCY
摘要 A method and apparatus for assuring the accuracy of data received by any device in a computer system from any other device in the same computer system or from another computer system. The existing hardware of a computer system is utilized to generate a cyclic redundant check character each time a unit of data is transmitted. The cyclic redundant check character is concatenated to the right of such data transmitted. Each time that the particular data is received, the check character and the data with which it is associated, is again manipulated in the same manner as in generating the check character. If the data received is the same as the data transmitted, the result of such manipulation is zero.
申请公布号 JPS5322341(A) 申请公布日期 1978.03.01
申请号 JP19770095647 申请日期 1977.08.11
申请人 HONEYWELL INF SYSTEMS 发明人 GARII JIEI GOOSU;ROBAATO SHII MIRAA
分类号 G06F11/10;H03M13/00;H03M13/09 主分类号 G06F11/10
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