Memory having cells each with three transistors - has source voltage to control electrode of second transistor during refresh condition at logical zero

摘要

The memory device consists of memory cells each containing three transistor memories. The input of the first transistor is connected to a word and a pit line. The output of this transistor is connected to the junction of the logic state of the cell which is connected to one of the main electrodes of the second and third transistors. The other main electrode of the third transistor is connected to a refresh line. The control electrode is connected to the other main electrode of the second transistor. This switching voltage source is connected to the control electrode of the second transistor. This will conduct during the refresh condition, if the junction voltage represents a logical nought. This means the third transistor will not conduct. If it represents a logical one this means the second transistor will not conduct and the third transistor will open via the voltage of the refresh line.