发明名称 PHASE DUTY ADJUSTING CIRCUIT
摘要 <p>PURPOSE:To simplify the circuit constitution by constituting the titled circuit by the 1st, 2nd multivibrators inputting the 1st clock signal and the 2nd and 3rd clock signals and a D flip flop inputting a data signal and the 2nd clock signal. CONSTITUTION:The multivibrators 10, 11 input a clock waveform 101 to adjust the duty depending on the change in the time constant as shown in signals 103,104,105 and 106,107,108, and output respectively inverted clock signals. The D flip-flop 12 inputs a data signal 102 and the signals 103, 104, 105 and outputs data signals 109,110,111 in matching with the phase with that of the clock signal. The duty of the obtained clock signal and the phase relation on request between the clock signal and the data signal are obtained by the combination of the time constant in the circuit.</p>
申请公布号 JPS62261244(A) 申请公布日期 1987.11.13
申请号 JP19860105597 申请日期 1986.05.08
申请人 NEC MIYAGI LTD 发明人 YUKI KAZUHIRO
分类号 H04L7/04;H03K5/00;H03K5/04;H03K5/13 主分类号 H04L7/04
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