| 摘要 |
1480138 Integrated circuits PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 3 July 1974 [6 July 1973 25 June 1974] 29480/74 Heading H1K [Also in Division H3] Each cell, e.g. 11 of a memory matrix comprises a pair of cross-coupled transistors 111, 112 of one conductivity type having respective collector load transistors 113, 114 of the other conductivity type, at least one of the bases of the cross-coupled transistors being connected via the main current path of a transistor 115 to a bit line B 0 , the bases of transistors 113, 114, 115, and the emitters of transistors 111, 112 being interconnected to a node 117. The circuit is characterized in that the emitters of the load transistors 113, 114 are connected to an associated row selection line X 1 , the bit line B 0 is connected to a column selection circuit Y, and the nodes of all cells are directly interconnected. In the embodiment of Fig. 1 a second bit line B 1 is connected to the base of transistor 112 via a further series transistor 116. In a modification, Fig. 11 (not shown), this second bit line and transistor 116 are omitted and the collector area of transistor 112 is made larger than that of transistor 111. The nodes, e.g. 117 are all coupled to a common current source S1 which normally divides equally between all cells. During write selection the current to the selected cell is made smaller than that to the other cells and vice versa during read selection. The matrix of Fig. 1 may be fabricated as an integrated circuit having the form of Figs. 2, 3 (not shown), Figs. 4, 5, 6, 7 (not shown) or Figs. 8, 9, 10 (not shown) and the matrix of Fig. 11 may be fabricated in the form of Figs. 12, 13 (not shown). In the arrangement described with reference to Figs. 8, 9, 10 (not shown) a lateral transistor having four collectors is utilized as four of the row selection transistors 72. Transistors 97, 94 may also be lateral transistors. |
