| 摘要 |
1534164 Master-slave flip-flop circuits PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 30 July 1976 [4 Aug 1975] 31826/76 Heading H3T In an electronic switching arrangement including a master-slave flip-flop 1, a charge-discharge circuit 5-12 is connected to a condition input of the flip-flop and is operated in a charge or discharge mode in dependence on a switch 8 and the operation of the arrangement is such that when the switch 8 is moved to its operating position 10 the condition input J, K is held at or beyond a threshold level (Fig. 2, not shown) for a period and if during that period a pulse train T from 2 applied to the flip-flop is in its first state this causes a change of condition in the master of the flip-flop and this change causes the state present at the output Q 1 of the flip-flop to be reversed when the pulse train goes to its second state (at t 1 ). The push-button switch 8 is normally biased as shown and when pressed (at t 0 ) a capacitor 6 is charged and the JK inputs are held at or beyond the threshold level for a period. A change in output at Q 1 under the conditions described above is indicated by a lamp 13 and can be used at 4 for control of a television camera and signal processing and video switching equipment. When pressing of the switch 8 ends (at t 3 ) the capacitor 6 discharges via resistors 5 and 11. When the switch 8 is again pressed (at t 5 ) to charge the capacitor the voltage at the JK inputs is at or beyond the threshold level when the pulse train T is in its first state (at t 6 ) and the condition of the master of the flip-flop is changed. When the pulse train T next goes to its second state (at t 8 ) the output Q 1 of the flip-flop is reversed. The input 3 can be supplied with a logic O blocking signal to inhibit output Q 1 from this flip-flop. Mutual locking between electronic switches of the kind shown in Fig. 1 can be obtained by connecting the Q 2 output of an electronic switch to the input 3 of another electronic switch so as to cause its flip-flop 1 to be blocked when a logic O is obtained on the Q 2 output. |
