| 摘要 |
1500169 Paging systems HASLER AG 9 July 1975 [11 July 1974] 28980/75 Heading G4H A paging system comprises a transmitter Fig. 1, and a plurality of receivers, Fig. 2, which can be called individually, the transmitter comprising a carrier frequency generator 1, for, e.g. 30-60 kHz, including means for frequency or phase modulation by a call signal generator 8, a call signal being composed of code words each containing the same number of signal elements, and capable of calling at least one receiver, and each receiver including a demodulator 26, a call signal detector, and an audio frequency signal generator 34 connected to an acoustic generator 36 and activated by the call signal detector, the transmitter and each receiver including a frequency divider 6, 30 respectively for the carrier frequency to provide timing signals. In an embodiment the transmitter further comprises an induction loop 5, and a key sender 9 for setting up the call signal, and the receiver comprises a phaselocked loop demodulator 26 feeding a decoder 33. A call signal commences with a 10 bit synchronization signal (13), Fig. 3 (not shown) and is followed by a 2-bit message (14) and then by the call address (15) consisting of five 4-bit words selected from the following five code words: A=0011, B=0110, C=1100, D=1001, E = 0101. The word E in an address stands for any of the other words A-D, so that group calls may be produced, the address EEEEE calling all receivers. The address is followed by a parity word (16). The phase-locked loop demodulator 26 provides as inputs to the decoder 33 the carrier frequency on 27, the data on 28 and a control signal on 29. The decoder 33 comprises a signal element counter (mod 4) (51), Fig. 4 (not shown), which generates (on 52) a code word timing signal, and controls a code matrix (56) which is set to the call signal assigned to the receiver. The code word timing signal feeds a code word counter (mod 8) (53) having outputs to seven AND gates (570-576) also connected to receive the call address from the code matrix (56) and an output from a parity checking circuit (43). A comparator circuit (54) delivers a first reset signal to a first flipflop (65) in the case of non-conformity between an element of the received address and the assigned address. The comparator includes means for comparing each received code word with the word E, and for non-conformity delivering a second reset signal to a second flipflop (66), both reset signals being delivered to an AND gate (67) the output of which resets the signal element counter (51), the code word counter (53) and also the carrier frequency divider 30. In the absence of either reset signal a further output of the code word counter (7, 41) activates audio generator 34. A message circuit (45) converts the message bits (14) into control signals which may operate a switch 38. The carrier frequency dividers 6, 30 may typically produce a timing pulse frequency of about 100 Hz, fluctuations due to frequency modulation of the carrier being the same for both transmitter and receiver.
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