| 摘要 |
<p>The system has a circuit which records and reads the speed of the vehicle and time counted with respect to the start of the cycle. A second circuit records and reads signals representing vehicle motion and distance measured with respect to the start of the cycle. The recording part of the first circuit has an addressable memory. The memory can be addressed by N(n+n') bits associated with a counter of capacity N(n+n'), n being the number of speed data and n' the number of time data forming a message. N is the number of messages that are to be memorised. The recording part of the second circuit has a memory addressable by Y(y+y') bits. These bits are associated with a counter of capacity Y(y+y'). y being the number of bits necessary for reading of the signals. Y' that necessary for recording of distance. Y the number of messages that are to be recorded.</p> |
