| 摘要 |
A multiple-generating register generates one of several possible multiples of a binary number which is input thereto depending upon the informational content of a 3-bit control signal. For each data stage there exists a data selector circuit, a master/slave circuit, and an output buffer circuit. The device can be configured as an inverting shift register for test and diagnostic purposes. The device is implemented in current mode logic, and a portion of the circuitry operates on differential level signals for increased operational speed and efficiency.
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