| 摘要 |
<p>A semiconductor memory or memory component having a matrix of cells in a semiconductor crystal divided into rows and columns, in which the individual cells may be addressed through the appropriate row or column leads, by the operation of a decoder associated with each, and in which the matrix is subdivided into two or more submatrixes with one or more additional decoders. Each submatrix may be addressed through a pair of decoders acting only for this submatrix. The arrangement replaces normal two-dimensional decoders by three or more dimensional arrangements. This permits a compact matrix to be designed in a compact space without the normal penalty of increased access time for a given storage capacity and improves the speed power product of the memory.</p> |
