| 摘要 |
This disclosure relates to a parallel speed regulator system for a plurality of d.c. motors operated on a common bus having a single armature electrical supply. The speed control, current limiting, and field current controllers for each motor are arranged in parallel and connected to a resistor-diode switching network to provide a switching order of priority: (1) maximum and minimum field current controllers (2) armature current limit controllers and (3) speed controller. This parallel speed regulator system provides all the inherent advantages of the multiloop controller arrangement together with automatic adjustments which are a function of the instantaneous motor operating point, so that the dynamic response of the motor remains the same regardless of perturbations in the operating points. |
