| 摘要 |
PURPOSE:To reduce the increase of the modulation speed required for maintaining the information transmission speed by simultaneously encoding only low-order two levels to prevent the increase of the number of error sequences and encoding only one of high-order levels and prohibiting the encoding of fourth or higher-order levels. CONSTITUTION:Digital data is inputted from a terminal 100 and carried to a speed converting circuit 101 and inputted to a serial/parallel converter 102. Data of low-order two levels out of parallel converted data is inputted to an error correction encoder 103, and an encoded output sequence is supplied to a signal converter 105. A third level is inputted to an error correction code encoder 104, and an encoded output sequence is supplied to the signal converter 105. Parallel converted data is supplied to the signal converter 105 as it is with respect to the data of fourth or higher-order levels. Thus, 2800Hz is enough though a conventional system requires 2860Hz as the modulation speed of the whole of the system. |
