发明名称 DIGITAL DATA STORAGE APPARATUS
摘要 1497680 Data storage systems INTERNATIONAL COMPUTERS Ltd 22 Oct 1975 [29 Oct 1974] 43290/75 Heading G4A A plurality of data blocks are serially recorded on each of a plurality of tracks of a recording medium 11, N read heads enter data from respective tracks into corresponding buffers 13 in parallel, and the buffers 13 are read out sequentially, one block from each buffer, onto an output path 17 at a data rate at least N times the average rate at which data is read from any individual track. By recording successive blocks of a sequence on different tracks, e.g. on the same cylinder of a disc file, a higher read-out rate is obtained. The blocks are preferably staggered from track to track. A sequencer 14 detects an identifier (ID) associated with each block, only one ID at a time appearing on channels CH owing to the blocks being staggered. Each ID contains cylinder, channel and block numbers for the associated data block, the channel number being decoded by sequencer 14 to control write-in to the appropriate buffer 13. Channel and block counters in sequencer 14 predict these numbers for the next block to be read and are incremented if a matching comparison is obtained with the next ID. Each buffer 13 includes a 4-bit serial to parallel converter feeding a shift register which has four bits per stage and is clocked in at “ of the channel data rate. Arrival of the end of the preamble, which precedes each data block, at the end of the shift register causes generation of a buffer full signal which inhibits further clocking in of the shift register. When the buffer is selected for read out by a signal CHR from output control 15 the shift register is read out by a high speed highway clock onto a 4-bit data highway 17. A counter in output control 15 produces a CHECK signal when check bits which accompany each data block are on highway 17, and this initiates a comparison between the check bits on highway 17 and check bits derived from the data by a check circuit 51. Further channel and block number counters in control 15 are preset when the first ID is read, the channel number being decoded to produce channel read-out select signals CHR commencing with the first channel on which a block was read.
申请公布号 GB1497680(A) 申请公布日期 1978.01.12
申请号 GB19750043290 申请日期 1975.10.22
申请人 INT COMPUTERS LTD 发明人
分类号 G06F3/06;G06F17/30;G11B20/12;G11B27/30;(IPC1-7):G11D1/00 主分类号 G06F3/06
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