| 摘要 |
<p>1457058 Data transmission; looped systems INTERNATIONAL BUSINESS MACHINES CORP 8 April 1974 [30 May 1973] 15431/74 Heading H4P To reduce interruption time in a communication system arranged on a closed loop, which may comprise two channels, wherein signals normally circulate unidirectionally on the or each channel, switch units are arranged to terminate ends of selected loop sections and duplicate an incoming data stream which is transmitted bi-directionally at a first unit the two identical streams being monitored and synchronized by delaying the earlier stream at a second unit. The delay of the earlier stream is increased incrementally each sync. character arrival if the phase is less than one time unit difference, which is further adjusted successively by fractions of a time unit. A main loop and auxiliary loop may be separate wire pairs or separate time space channels. Normally data circulates unidirectionally on loop 11 to which interface units and terminals are connected, and oppositely on loop 13, the loops normally being independent but may be sectioned and loop ends mutually connected in fault conditions by units 21. Loop controller 19 generates a sequence of empty frames which can be seized and used for transmission by any terminal. If failures are recognized early, switch over can be made in controlled manner to avoid interruptions. Each switch unit 21 comprises sync. circuitry 23, receiver/transmitter 25, 27, and further circuitry (see Fig. 4, not shown) for connection or disconnection of power supply. Sync switching circuit 23 comprises switches S11, S12, S21, S22 by which main loop sections 29, 31 and auxiliary sections 33, 35 may be selectively connected and controlled by unit 39, which receives commands either via main loop and Rec/Trans 25 or auxiliary loop through Rec/Trans 27. Discriminator 41 detects time difference between frame arrivals on the loops and variable delays 43, 45 controlled by 39 incrementally vary the delay to provide near coincidence of the two streams. The discriminator is described with reference to Fig. 7 (not shown). The beginning of each frame has a sync. pattern for synchronizing purposes and clock signals are derived from the data stream by unit 39. For fine adjustment, monostable circuits 83, 85 and AND 87 are provided. When phase difference has been reduced to less than one bit period, loop controller shifts leading end of the frames on the auxiliary loop fractions, e.g. 1/10th bit period both positively and negatively so that time difference approximates to zero. Delay unit (Fig. 8, not shown) comprises a shift register (95) operating in conjunction with a control register which selects one of several output stages from register 95 and hence the delay. The switch units may facilitate fault location but this aspect is not particularly described.</p> |
