SOLID STATE FAIL-SAFE LOGIC SYSTEM

摘要

A solid state fail-safe logic system is disclosed including AND and OR gates which are designed as an evolutionary replacement for signal control functions previously performed by vital front and back contacts of vital relays and power check logic. The AND gate is basic and accepts an a.c. and a d.c. input. The a.c. input circuit includes a light emitting diode optically coupled to a light receiving active circuit means. Leakage currents cannot falsely activate the gate since the light emitting diode is poled to be reverse biased by the supply voltage. The d.c. input is protected from leakage currents by proper connections so that any leakage current is of the wrong polarity to produce an output. The d.c. input provides forward bias for light responsive active circuit means. The AND gate is divided into an input module including the light emitting diode and an output module inciuding the light responsive active circuit means. An OR gate is provided by using an AND gate output module and one AND gate input module for each OR gate input.