COMPUTER

摘要

1499598 Data processing HOLLANDSE SIGNAALAPPARATEN BV 12 June 1975 [24 June 1974] 25216/75 Heading G4A A computer comprises a plurality of memory units, 1A-1M, and a like plurality of memory control units 3A-3M each connected to all of a number of central processors 4a-4k and to respective input/output control units 5A l -5A n ... 5M l -5M n , the sum, n, of the number of central processors and the number of input/ output control units connected to each memory control unit 3A-3M being equal to the ratio of the cycle time of each central processor and input/output control unit to the cycle time of each memory unit. Thus each central processor 4a-4k is connected to all the memory units 1A-1M during every nth memory unit cycle and each input/output control unit is connected to the respective memory unit during every nth memory unit cycle. n may be two, there being two memory units 1A, 1B, two memory control units 3A, 3B, one central processor 4a and two input/output control units 5A 1 , 5B 1 .