| 摘要 |
<p>A method and apparatus for digital frequency synthesis is provided which enables the channel spacing of a digital synthesizer to be decreased below a reference frequency. The frequency clock output of a voltage controlled oscillator is digitally divided by an average multiple which may be other than a whole number. The output of the divider forms the input to a digital phase comparator which compares the phase of the reference frequency and the input or feedback frequency and generates a signal output that has a duty cycle proportional to the phase difference between the reference and feedback frequencies. The last mentioned output signal eventually is used to bias the voltage controlled oscillator to the proper output frequency so that the feedback and reference frequencies have a constant phase difference. Since the average multiple of the divider can be varied fractionally, a plurality of output signals from the voltage controlled oscillator are obtainable which have frequency spacing between them of some frequency less than the reference frequency.</p> |
