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发明名称
TEST METHOD FOR IC MEMORY
摘要
PURPOSE:To improve the reliability, by detecting the defective function due to the phase difference among a plural number of input terminals, thru the provision of the exclusive logical sum gate with the output of IC memory tester.
申请公布号
JPS52155926(A)
申请公布日期
1977.12.24
申请号
JP19760072153
申请日期
1976.06.21
申请人
HITACHI LTD
发明人
UCHIYAMA TAKEO
分类号
G11C11/413;G01R31/28;G06F11/24;G11C7/24;G11C29/00;G11C29/56
主分类号
G11C11/413
代理机构
代理人
主权项
地址
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