Timing generator for carrier systems using pilot tone control - has counter lock circuit operating with asymmetrical clock pulses

摘要

The timing generator for pilot-tone regulators in carrier-frequency transmission systems, has a built-in locking facility to prevent instability in the control counter. The output of the level detector (PD) in the pilot tone control loop, controls the clock-pulse generator (TG) and also the J and K inputs of the counter (Z). The base of a transistor (Tx) is connected via a differentiating capacitor (C2) to the output of the clock generator. The collector is connected to the clock input of the counter (T) and an integrating capacitor (C1) is connected to the emitter. During the control cycle, should the outputs of the level detector be energised, a cloc pulse is derived by the transistor stage through differentiation of the trailing edge of the clock pulse and integration of the leading edge. This clock signal has short positive and long negative pulses.