发明名称 READOUT APPARATUS FOR FREQUENCY OR PERIODANALOGUE MEASURING SIGNALS
摘要 1495566 Counting apparatus PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 31 Dec 1974 [4 Jan 1974] 56157/74 Heading G4D In measuring systems, of the kind comprising a transducer delivering pulses at a rate related to the value of a variable and a counter responsive to the pulses to reach, at the end of a measuring period, a count forming a direct readout of the said value, a reversible counter is used which at the start of the measuring period is preset to a count Z 1 representing a given value of the variable and is then caused to count up during a first period a number of pulses dependant on the value sensed by the transducer and to count down during a second period a number of pulses dependant on the given value. In a first embodiment (Fig. 1), in which the output frequency f m of the transducer is directly proportional to the value sensed, the reversible counter C has the transducer pulses applied to its up input and pulses from an oscillator 0 to its down input (the frequency fr of the oscillator having previously been set equal to f M when the transducer senses a value equal to Z 1 ). The pulses are applied concurrently, overlapping pulses being eliminated by a synchronizing circuit S, and for equal periods controlled by gates Gu, Gd enabled by a control counter CT which counts down by clock pulses fc from a preset value Z 2 . The value Z 2 , and therefore the length of the counting period, is set previously to ensure that counter C reaches the correct value when a second given value is sensed, i.e. the scale is correct. The control counter CT also controls gates Gz and G D to preset the counter C at the start and read it out to a display D at the end of the period. A second embodiment (Fig. 3, not shown) employs the same components but with the inputs f M , f r , f c differently applied and the gates G u , Gd differently enabled. In this embodiment the output frequency of the transducer is indirectly proportional to the value sensed. The counter C counts clock pulses fc up for the first period and down for the second period, consecutively. The two periods are made proportional to f M and f r by causing control counter CT to count transducer pulses to determine the first period and to count the same number of oscillator pulses f r to determine the second period, the number of pulses being adjusted to obtain the correct scale. In a modification counter CT is replaced by two separate counters counting f M and f r respectively so the up and down counts again proceed concurrently. A modification is described (Fig. 6, not shown) for dealing with measured values less than the first given value simply involving automatically reversing the connections to the updown inputs of the counter. Where the up/down counts are performed consecutively and a large capacity counter is employed only the lower order stages need be read by the display (Fig. 5, not shown).
申请公布号 GB1495566(A) 申请公布日期 1977.12.21
申请号 GB19740056157 申请日期 1974.12.31
申请人 PHILIPS ELECTRONIC & ASS IND LTD 发明人
分类号 G01R23/10;G01R23/09;H03M1/00 主分类号 G01R23/10
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