| 摘要 |
A method and apparatus for compressing test vector data for use in testing a logic product, wherein original test vector data is generated in the form of two or more sequences of bits including "care" bits and "don't care" bits. The test vector data is then compressed by comparing corresponding bits of two or more subsequent vectors and merging the two or more vectors into a single vector representative thereof if all of the corresponding bits of the two or more vectors are found to be compatible. Compatibility of two bits is achieved if they do not have specifically incompatible or opposite values. <IMAGE> <IMAGE> |
