Vertical synchronizing circuit

摘要

A vertical synchronizing circuit wherein a counter counts pulses at twice the horizontal deflection rate and provides a vertical output pulse at a predetermined count is shown. A synchronism or mode detector causes the circuit to switch to a driven mode when the counter is not reset in synchronism with the vertical synchronizing pulses. The mode detector causes the circuit to switch to a countdown mode when synchronism is detected. A phase detector detects phase errors between the counter and the vertical synchronizing pulses when the circuit is in the countdown mode and causes the counter to delete or add counts depending upon the direction of the phase error when such phase errors persist for a predetermined number of vertical fields. The vertical synchronizing pulses are applied to a gate which is enabled in the countdown mode when the counter reaches a predetermined count shortly before a vertical synchronizing pulse is anticipated. An auxiliary counter counts pulses and is reset by each vertical output pulse. In the driven mode the synchronizing pulse gate is enabled at a predetermined earlier count of the auxiliary counter. The auxiliary counter also provides the vertical output pulse at a predetermined count if a vertical output pulse is not otherwise provided.