| 摘要 |
<p>A shift register is used with such a large number of stages and such high shifting frequency, than an answering pulse of nomal duration occupies n stages. Pulse frame decoding and passive decoding of answer signals are provided. Decoder pulse obtained by passive decoding and signalling correct answer coding and affected by jitters, is extended and applied in this shape to an AND gate. A frame pulse, pref, the F2 pulse, is delayed by a certain time corresponding to processing time of the decoder and following in circuit components up to formation of the delayed decoder pulse. A pulse appearing at the AND gate output owing to coincidence of these two pulses is used as output pulse for further processing.</p> |
