FREQUENCY PHASE COMPARATOR

摘要

1519491 Phase comparator MOTOROLA Inc 23 May 1975 [5 Aug 1974] 22791/75 Heading H3A In a phase comparator a reference pulse train J and a pulse train H are applied to circuitry 20 which generates pulse trains L, N, M to successively enable gates 60, 63, 70 so that a voltage source V S is connected to a voltage store (e.g. capacitor 62) for a time proportional to the amount pulses J lead pulses H in phase, the stored voltage being sampled by pulses N and then removed by pulses M. Successive voltages V 62 on capacitor 62 are accumulated on a capacitor 65, the voltage on which may be applied to the variable frequency source (e.g. a voltage controlled oscillator). Pulses J are obtained via flip-flops 11-16 and a gate 17 from a pulse train A and are applied with pulses H to a flip-flop 31. The H pulse length is slightly less than half the J pulse length. When the leading edge of an H pulse lies within a J pulse (I. Fig. 2), the width of pulse L is such that capacitor 62 is charged to between O and V S . When the H pulse leading edge follows the J pulse trailing edge (i.e. the H frequency drops), pulse L is longer and capacitor 62 charges to its maximum V S (II, Fig. 2). When the H pulse leading edge precedes the J pulse leading edge (i.e. the H frequency rises), no L pulse is generated and capacitor 62 is not charged (III. Fig. 2). In these latter two cases, gates 33. 34 etc. provide set and reset pulses R. S to predetermined ones of flip-flops 11-16 to force the next J pulse to appear at approximately the correct time to coincide with the centre frequency of pulses H (thus the comparator cannot lock onto harmonics). Gates 60, 63 70 may be semiconductor transmission gates and the comparator circuit may be formed as an IC using CMOS components.