Apparatus and method for vector instructions for large integer arithmetic

摘要

An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.

主权项

1. A method comprising:
decoding a first instruction, a second instruction, a third instruction, a fourth instruction, and a fifth instruction with a hardware decoder of a hardware processor; executing the first instruction with a hardware execution unit of the hardware processor to multiply a first input operand and a second input operand and present a lower portion of a result, said first input operand representing a first digit of a multiplier, said second input operand representing a first digit of a multiplicand; executing the second instruction with the hardware execution unit of the hardware processor to multiply said first input operand and said second input operand and present an upper portion of a result; executing the third instruction with the hardware execution unit of the hardware processor to multiply said first input operand and a third input operand and present a lower portion of a result, said third input operand representing a digit of said multiplicand that neighbors said first digit of said multiplicand; executing the fourth instruction with the hardware execution unit of the hardware processor to multiply said first input operand and said third input operand and present an upper portion of a result; and executing the fifth instruction with the hardware execution unit of the hardware processor to add aligned digits of the upper and lower portions and record a carry term in a mask register.