| 摘要 |
1459492 Synchronizing counters COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 14 Jan 1974 [12 Jan 1973] 01679/74 Heading G4D In an apparatus for bringing counters A, B, C into synchronism individual digits of the counters having the same weight are compared in comparators CO1, CO2, CO4 respectively (for binary digits of weights 1, 2, 4 respectively); the counters to be corrected are selected automatically and the correction is applied by a control unit W which is set in operation by an externally applied signal MP and cancelled when the counters are in synchronism. When any of the comparators CO1-CO4 detects an inequality then a selecting circuit TI1-TI4, corresponding to the highest weight in which there is an inequality, is operated and selects at SA, SB, SC those counters having the lower count; the lower weight circuits TI1-TI4 are inhibited by diode connections (D1-D9, Fig. 2, not shown). The control circuit W contains a bi-stable circuit and an astable multivibrator. When the external signal is applied the bi-stable is set and allows the astable to begin oscillating. At each oscillation, circuits RA, RB, RC corresponding to the selected terminals SA, SB, SC send pulses to the selected counters to advance their count. When the digits of highest weight are equal the next lower selecting circuit TI1- TI4 is operated to release further pulses to the counters and so on until all weights of the counters are synchronized. When no comparators CO1-CO4 give an output a circuit TE issues a signal SE to reset the bi-stable. Detailed transistor circuits of the units CR and RP are described (Figs. 2-5, 7, not shown). A simplified version is also described for synchronizing just two counts (Fig. 6, not shown). |
