发明名称 DATA TRANSFER SYNCHRONOUS DIGITAL LOGICAL CIRCUIT
摘要 <p>A digital logic circuit synchronizing data transfers between asynchronously clocked data systems. Synchronization is accomplished by three logically interlocked storage elements which respectively record and control (1) the time when data is available for transfer, (2) time when data transfer begins and (3) the time when data transfer is complete. Transfer is accomplished without a loss of data independent of the clock pulse width and frequency relationship of the asynchronously clocked systems.</p>
申请公布号 JPS52134340(A) 申请公布日期 1977.11.10
申请号 JP19770047496 申请日期 1977.04.26
申请人 MOTOROLA INC 发明人 EDOWAADO KUREA HETSUPUWAASU;ROTSUDONIII JIEROOMU MIINZU
分类号 G06F1/12;G06F5/08;G06F13/38;G06F13/42 主分类号 G06F1/12
代理机构 代理人
主权项
地址