发明名称 Memory control system using plural buffer address arrays
摘要 In a data processing system in which a single main memory is shared by two or more basic processing units, each unit is provided with a first buffer address array which stores the addresses of data stored in the associated buffer memory and is searched by this processing unit and with second buffer address arrays which store the copy of the content of the first buffer address array and are searched by the store addresses from the other processing units, so that the information stored in the buffer memory of one processing unit may be prevented from becoming different from the information stored in the main memory when another processing unit performs a storing operation, without degrading the processing efficiency of the system.
申请公布号 US4056844(A) 申请公布日期 1977.11.01
申请号 US19750620757 申请日期 1975.10.08
申请人 HITACHI, LTD. 发明人 IZUMI, CHIKAHIKO
分类号 G06F12/08;G06F15/16;G06F15/177;(IPC1-7):G06F13/00 主分类号 G06F12/08
代理机构 代理人
主权项
地址