MEMORY CELL

摘要

1509796 Memory arrangement HONEYWELL Inc 24 April 1975 [25 April 1974] 16968/75 Heading G4C A memory includes a matrix of flip-flop storage elements X11-X22, two bit lines AB, BB for each column of the matrix and two word lines 70, 72 for each row; to write a word into a selected row of the matrix a write select decoder WS places a "1" on word lines 70 and 72 of the selected row and a signal is applied to a terminal WE to enable gates 74, 78 to pass the bits of the word, applied to terminals WD, to the first bit lines AB and their complements to second bit lines BB; to read a word from a selected row of the matrix on to the bit lines AB or BB and thence directly and via inverters 60 or 64 to an output channel RAD or RBD a read select decoder RAS or RBS places a "1" on the word line 70 or 72 of the selected row. Two words may be read out simultaneously, to output channels RAD, RBD, for processing by a processing unit. Each flip-flop storage element X11-X22 includes four cross-coupled field-effect transistors (50, Fig. 2, not shown) the first bit line AB being connected to one side via a gate (66) controlled by the first word line 70 and the second bit line BB being connected to the other side via a gate (68) controlled by the second word line 72.