| 发明名称 |
MEANS FOR COORDINATING ASYNCHRONOUS MAIN STORE ACCESSES IN A MULTIPROCESSING SYSTEM G VIRTUAL STORAGE |
| 摘要 |
<p>A unique control circuit that maintains the addressability to an invalidated page frame until execution is completed for all current instructions in all CPUs of a multiprocessing system which uses demand-paging and virtual addressing.</p> |
| 申请公布号 |
CA1019453(A) |
申请公布日期 |
1977.10.18 |
| 申请号 |
CA19740214174 |
申请日期 |
1974.11.19 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
PADEGS, ANDRIS;SMITH, RONALD M. |
| 分类号 |
G06F12/00;G06F12/10;G06F12/14 |
主分类号 |
G06F12/00 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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