KOPPLINGSANORDNING FOR REGLERING AV PULSTAKTEN FOR EN SIGNAL

摘要

A circuit arrangement is described wherein the pulse repetition frequency of a signal is digitally controlled in dependence on the pulse repetition frequency of a controlling signal. A presettable digital counter functioning as a frequency divider operates between preset initial and end counts and is reset to the initial value each time the end value is reached; the initial and end values are set responsive to binary signals applied to control inputs of the counter. A bistable trigger stage assumes either an idle or an operative state in dependence on the value of a control signal derived from the controlling pulse repetition frequency and a timing signal. The trigger stage output is used to control either the setting of the afore-mentioned initial value or the end value to produce either too high or too low values for the pulse repetition frequency of the controlled signal.