Low power consumption cyclic dynamic memory - uses clock pulses split into closely spaced narrow pulse pairs

摘要

A circuit for a cyclically operating dynamic memory, esp. for telephone exchanges, uses stored data returned to the input through a logic circuit. The memory has two separate shift registers operating alternately under the control of two separate sets of clock pulses, each pulse acting as the input pulse for one register and the output pulse for the other, by the falling and rising flanks respectively. The clock pulses of both series consist of a pair of very short pulses with the space between the rising flank of the first pulse and the falling flank of the second pulse less than the spacing between two alternating clock pulse pairs but equal to at least the sum of the max. read-out time at max. operating time of the logic circuit and the max. storage time.